Verilog HDL锁存器实现

（1）异步高电平有效

module async_latch_H(
  input C,S,  //Set Q to 1, Clear Q to 0
  output reg Q
);


always @(*)
begin 
  if(C)
    Q <= 1’b0;
  else if(S)
    Q <= 1’b1;
  else
    Q <= Q;
end


endmodule 

（2）异步低电平有效

module async_latch_L(
  input S, C,  //Set Q to 1, Clear Q to 0
  output reg Q
);


always @(*)
begin 
  if(~C)
    Q <= 1’b0;
  else if(~S)
    Q <= 1’b1;
  else
    Q <= Q;
end


endmodule 

（3）同步高电平有效

module sync_latch_H(
  input clk, S, C,  //Set Q to 1, Clear Q to 0
  output reg Q
);


always @(posedge clk)
begin 
  if(C)
    Q <= 1’b0;
  else if(S)
    Q <= 1’b1;
  else
    Q <= Q;
end


endmodule 

module sync_latch_L(
  input clk, S, C,  //Set Q to 1, Clear Q to 0
  output reg Q
);


always @(negedge clk)
begin 
  if(C)
    Q <= 1’b0;
  else if(~S)
    Q <= 1’b1;
  else
    Q <= Q;
end


endmodule 







审核编辑：刘清